View FAN5109MX_1238750.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FAN5109 Dual Bootstrapped 12V MOSFET Driver
October 2005
FAN5109 Dual Bootstrapped 12V MOSFET Driver
Features
Drives N-channel High-Side and Low-Side MOSFETs
General Description
The FAN5109 is a high-frequency driver, specifically designed to drive N-Channel power MOSFETs in a synchronous-rectified buck converter. This driver, combined with a Fairchild Multi-Phase PWM controller and power MOSFETs, form a complete core voltage regulator solution for advanced microprocessors. The FAN5109 drives the upper and lower MOSFET gates of a synchronous buck regulator up to 12VGS. The FAN5109's output drivers can efficiently switch power MOSFETs at frequencies above 500kHz. The circuit's adaptive shoot-through protection prevents the MOSFETs from conducting simultaneously. The FAN5109 is rated for operation from 0C to +85C and is available in a low-cost SOIC-8 package.
in a Synchronous Buck Configuration Enhanced Upgrade to FAN5009 Direct Interface to FAN5019B/FAN5182 and other compatible PWM Controllers 12V High-Side and 12V Low-Side Drive Internal Adaptive "Shoot-Through" Protection Fast Rise and Fall times Switching Frequency above 500kHz OD input for Output Disable - allows for synchronization with PWM Controller SOIC-8 Package
Applications
Multi-phase VRM/VRD Regulators for Microprocessor
Power
High Current/High Frequency DC/DC Converters High Power Modular Supplies
Ordering Information
Part Number
FAN5109MX
Temperature Range
0C to 85C
Pb-Free
Yes
Package
SOIC-8
Packing
Tape and Reel
Qty/Reel
2500
Note: Contact Fairchild Sales for availability of leaded parts.
(c)2004 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
FAN5109 Dual Bootstrapped 12V MOSFET Driver
Typical Application
12V
FAN5109
4
VCC D1 CVCC
1
BOOT Q1 CBOOT
PWM
2
8
HDRV SW Q2 L1 VOUT
OD
3
OVERLAP PROTECTION CIRCUIT
7
VCC
5
COUT LDRV PGND
6
Figure 1. Typical Application
Pin Configuration
BOOT PWM OD VCC 1 2 3 4 FAN5109 8 7 6 5 HDRV SW PGND LDRV
Figure 2. 8-Pin SOIC Package
Pin Definitions
Pin #
1 2 3 4 5 6 7 8
Pin Name
BOOT PWM OD VCC LDRV PGND SW HDRV
Pin Function Description
Bootstrap Supply Input. Provides voltage supply to the high-side MOSFET driver. Connect to bootstrap capacitor and diode. PWM Signal Input. Accepts a logic-level PWM signal from the controller. Output Disable. When low, this pin disables FET switching (HDRV and LDRV are held low). Power Input. +12V bias power. Bypass with a 1F ceramic capacitor. Low Side Gate Drive Output. Connect to the gate of the low-side power MOSFET(s). Power Ground. Connect directly to the source of low-side MOSFET(s) and CVCC. Switch Node Input. Connect as shown in Figure 1. SW provides return for the high-side bootstrapped driver and acts as a sense point for the adaptive shoot-thru protection. High Side Gate Drive Output. Connect to the gate of the high-side power MOSFET(s).
2
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
FAN5109 Dual Bootstrapped 12V MOSFET Driver
Functional Block Diagram
VCC
4
VCC BOOT HDRV
OD PWM
2 3
1 8
+
VCC/3 1.3V
7
SW
1.3V VCC
5 6
LDRV PGND
Figure 3. Functional Block Diagram
3
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
FAN5109 Dual Bootstrapped 12V MOSFET Driver
Absolute Maximum Ratings
Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually, not in combination. Unless otherwise specified, voltages are referenced to PGND.
Parameter
VCC to PGND PWM and OD pins SW to PGND BOOT to SW BOOT to PGND HDRV LDRV Continuous Transient ( t=200nsec)
Notes: 1. For transient derating beyond the levels indicated, refer to the graphs on page 9.
Min.
-0.3 -0.3 Continuous Transient ( t=100nsec, F 500kHz) Continuous Transient ( t=100nsec, F 500kHz) VSW-1 -0.5 -2(1) -1 -5(1) -0.3 -0.3
Max.
15 5.5 15 25 15 30 38(1) VBOOT+0.3 VCC VCC+0.3
Unit
V V V V V V V V V V
Thermal Information
Parameter
Junction Temperature (TJ) Storage Temperature Lead Soldering Temperature, 10 seconds Vapor Phase, 60 seconds Infrared, 15 seconds Power Dissipation (PD) TA = 25C Thermal Resistance, SO8 - Junction to Case JC Thermal Resistance, SO8 - Junction to Ambient JA 40 140
Min.
0 -65
Typ.
Max.
150 150 300 215 220 715
Unit
C C C C C mW C/W C/W
Recommended Operating Conditions
Parameter
Supply Voltage VCC Ambient Temperature (TA) Junction Temperature (TJ)
Conditions
VCC to PGND
Min.
10 0 0
Typ.
12
Max.
13.5 85 125
Unit
V C C
4
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
FAN5109 Dual Bootstrapped 12V MOSFET Driver
Electrical Specifications
VCC = 12V, and TA = 25C using the circuit in Figure 4 unless otherwise noted. The * denotes specifications which apply over the full operating temperature range.
Parameter
Input Supply VCC Voltage Range VCC Current OD Input Input High Voltage Input Low Voltage Input Hysteresis Input Current Propagation PWM Input Input High Voltage Input Low Voltage Input Current High-Side Driver Output Resistance, Sourcing Source Current2 Output Resistance, Sinking Sink Current2 Transition Times2,4 Propagation Delay2,3 Delay2
Symbol
VCC ICC VIH (OD) VIL (OD) IOD tpdl(OD) tpdh(OD) VIH(PWM) VIL(PWM) IIL(PWM) RHUP RHDN tR(HDRV) tF(HDRV) tpdh(HDRV) tpdl(HDRV)
Conditions
* OD = 0V * * * * OD = 3.0V See Figure 5 *
Min.
6.4
Typ.
12 2.5
Max.
13.5 4
Unit
V mA V
2.5 0.8 550 -300 25 15 +300 40 30
V mV nA ns ns V
* * * VBOOT - VSW = 12V VDS = -10V VBOOT - VSW = 12V VDS = 10V Figure 4 See Figure 6
3.5 0.8 -1 2.5 2.0 1.1 3.0 25 15 40 25 2.0 40 25 55 40 2.6 1.2 30 25 30 25 1.5 +1 3.3
V A A A ns ns ns ns A A ns ns ns ns ns
Low-Side Driver Output Resistance, Sourcing Source Current2 Output Resistance, Sinking Sink Current2 tR(LDRV) tF(LDRV) Propagation Delay2,3 tpdh(LDRV) tpdl(LDRV) tpdh(LDF) See Adaptive Gate Drive Circuit description (page 10) See Figure 6 Transition Times2,4 RLDN VDS = 10V Figure 4 RLUP VDS = -10V 2.7 0.9 3.5 20 15 20 15 160
Notes: 1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control. 2. Specifications guaranteed by design/characterization (not production tested). 3. For propagation delays, "tpdh" refers to low-to-high signal transition and "tpdl" refers to high-to-low signal transition. 4. Transition times are defined for 10% and 90% of DC values.
5
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
FAN5109 Dual Bootstrapped 12V MOSFET Driver
12V 33K
FAN5109
1 BOOT 2 PWM 3 OD HDRV 8 SW 7 PGND 6 LDRV 5 3 nF 3 nF
10K
4 VCC 1F
Figure 4. Test Circuit
OD
VIL(OD) tpdl(OD)
VIH(OD)
tpdh(OD)
LDRV / HDRV
Figure 5. Output Disable Timing
VIH(PWM)
PWM
t pdl (LDRV)
VIL(PWM) t pdh(LDF)
LDRV
1.3V
t pdh(HDRV)
t pdl (HDRV)
HDRV-SW
t pdh(LDRV)
SW
VCC 3
Figure 6. Adaptive Gate Drive Timing
6
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
FAN5109 Dual Bootstrapped 12V MOSFET Driver
Typical Characteristics
Gate Drive Rise and Fall Times (1)
Gate Drive Rise and Fall Times (2)
40 35 Rise/Fall Time (nsec) 30 25 20 15 Fall 10 5 0 0 1000 2000 3000 4000 5000 Rise
40 35 Rise/Fall Time (nsec) 30 25 20 15 10 5 0 0 1000 2000 3000 4000 5000 CLOAD (pf) Fall
Rise
CLOAD (pf)
HDRV Rise/Fall Times vs. CLOAD
LDRV Rise/Fall Times vs. CLOAD
1.4 1.3
1.4 1.3 RLDRV (normalized) 1.2 1.1 1 0.9 0.8 -25
RHDRV (normalized)
1.2 1.1 1 0.9 0.8 -25
Source Sink
Source Sink
0
25 50 75 Temperature (C)
100
125
0
25 50 75 Temperature (C)
100
125
HDRV Normalized Impedance vs. Temperature
LDRV Normalized Impedance vs. Temperature
7
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
FAN5109 Dual Bootstrapped 12V MOSFET Driver
Typical Performance Characteristics (continued)
3000 2500 12 Vgs 2000 ID (mA) 10 Vgs 1500 8 Vgs 1000 6 Vgs 500 0 0 2 4 6 VDS (V) 8 10 12
500 0
0 2 4 6 8 10 12
3000 12 Vgs 2500 10 Vgs 2000
ID (mA)
1500 1000 6 Vgs
8 Vgs
VDS (V)
HDRV Pull-Up (Sourcing)
LDRV Pull-Up (Sourcing)
4000 3500 12 Vgs 3000 10 Vgs ID (mA) 8 Vgs 6 Vgs 2000 1500 1000 500 0 0 2 4 6 VDS (V) 8 10 12
ID (mA)
4000 3500
12 Vgs 10 Vgs
3000 2500 2000
6 Vgs
8 Vgs
2500
1500 1000 500 0 0 2 4 6 VDS (V) 8 10 12
HDRV Pull-Down (Sinking)
LDRV Pull-Down (Sinking)
8
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
FAN5109 Dual Bootstrapped 12V MOSFET Driver
Typical Performance Characteristics (continued)
-13 -12 -11 -10 VSW (V) -9 -8 -7 -6 -5 -4 -3 0 100 200 300 400 500 Transient Duration (nsec) SOA VLDRV (V) -5.0 -4.0 -3.0 -2.0 SOA SOA -1.0 0.0 0 100 200 300 400 500 Transient Duration (nsec) -6.0
Negative SW Voltage Transient
Negative LDRV Voltage Transient
35 30 15 Vcc 25 Icc (mA) 12 Vcc 20 15 6 Vcc 10 5 0 0 100 200 300 400 500 Frequency (KHz)
Operating Current vs. Frequency
ICC [mA] = VCC (0.26 + 3.38 FSW) where F SW is in MHz
9
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
FAN5109 Dual Bootstrapped 12V MOSFET Driver
Circuit Description
The FAN5109 is a driver optimized for driving N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. For a more detailed description of the FAN5109 and its features, refer to the Typical Application Diagram (Figure 1) and Functional Block Diagram (Figure 3).
(tpdl(HDRV)). Once the SW pin falls below ~VCC/3, Q2 begins to turn ON after an adaptive delay tpdh(LDRV). Additionally, VGS of Q1 is monitored. When VGS(Q1) is discharged below ~1.3V, a secondary adaptive delay is initiated, which results in Q2 being driven ON after tpdh(LDF), regardless of the SW state. This function is implemented to ensure CBOOT is recharged after each switching cycle, particularly for cases where the power convertor is sinking current and the SW voltage does not fall below the VCC/3 adaptive threshold. Secondary delay tpdh(LDF) is longer than tpdh(LDRV).
Low-Side Driver
The FAN5109's low-side driver (LDRV) is designed to drive ground referenced low RDS(on) N-channel MOSFETs. The bias for LDRV is internally connected between VCC and PGND. When the driver is enabled, the driver's output is 180 out of phase with the PWM input. When the FAN5109 is disabled (OD = 0V), LDRV is held low.
Application Information
Supply Capacitor Selection
For the supply input (VCC) of the FAN5109, a local ceramic bypass capacitor is recommended to reduce the noise and to supply the peak current. Use at least a 1F, X7R or X5R capacitor. Keep this capacitor close to the FAN5109's VCC and PGND pins.
High-Side Driver
The FAN5109's high-side driver (HDRV) is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit, consisting of an external diode and bootstrap capacitor (CBOOT) . During start-up, SW is held at PGND, allowing CBOOT to charge to VCC through the diode. When the PWM input goes high, HDRV will begin to charge the high-side MOSFET's gate (Q1). During this transition, charge is transferred from CBOOT to Q1's gate. As Q1 turns on, SW rises to VIN, forcing the BOOT pin to VIN +VC(BOOT), which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling HDRV to SW. CBOOT is then recharged to VCC when SW falls to PGND. HDRV output is in phase with the PWM input. When the driver is disabled, the high-side gate is held low.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (CBOOT) and an external diode, as shown in Figure 1. These components should be selected after the highside MOSFET has been chosen. The required capacitance is determined using the following equation: QG C BOOT = --------------------V BOOT (1)
where QG is the total gate charge of the high-side MOSFET, and VBOOT is the voltage droop allowed on the high-side MOSFET drive. For example, the QG of the FDD6696 MOSFET is about 35nC @ 12VGS. For an allowed droop of ~300mV, the required bootstrap capacitance is 100nF. A good quality ceramic capacitor must be used. The average diode forward current, IF(AVG), can be estimated by: I F ( AVG ) = Q GATE x F SW (2)
Adaptive Gate Drive Circuit
The FAN5109 embodies an advanced design that ensures minimum MOSFET dead-time while eliminating potential shoot-through (cross-conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive, adaptively, to ensure they do not conduct simultaneously. Refer to "Gate Drive Rise and Fall Times" waveforms on page 7 for the relevant timing information. To prevent overlap during the low-to-high switching transition (Q2 OFF to Q1 ON), the adaptive circuitry monitors the voltage at the LDRV pin. When the PWM signal goes HIGH, Q2 will begin to turn OFF after some propagation delay as defined by tpdl(LDRV) parameter. Once the LDRV pin is discharged below ~1.3V, Q1 begins to turn ON after adaptive delay tpdh(HDRV). To preclude overlap during the high-to-low transition (Q1 OFF to Q2 ON), the adaptive circuitry monitors the voltage at the SW pin. When the PWM signal goes LOW, Q1 will begin to turn OFF after some propagation delay
where FSW is the switching frequency of the controller. The peak surge current rating of the diode should be checked in-circuit, since this is dependent on the equivalent impedance of the entire bootstrap circuit, including the PCB traces.
Layout Considerations
Use the following general guidelines when designing printed circuit boards (see Figure 7 on the next page): 1. Trace out the high-current paths and use short, wide (>25 mil) traces to make these connections. 2. Connect the PGND pin of the FAN5109 as close as possible to the source of the lower MOSFET.
10
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
FAN5109 Dual Bootstrapped 12V MOSFET Driver
3. The VCC bypass capacitor should be located as close as possible to VCC and PGND pins. 4. Use vias to other layers when possible to maximize thermal conduction away from the IC.
CBOOT
1 2 3 4 8 7 6 5
CVCC
Figure 7. Recommended layout for SOIC-8 package (not to scale)
11
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
FAN5109 Dual Bootstrapped 12V MOSFET Driver
Mechanical Dimensions
0.150, 8 Lead SOIC Package
Symbol A A1 B C D E e H h L N ccc Inches Min. .053 .004 .013 .0075 .189 Max. .069 .010 .020 .010 .197 Millimeters Min. 1.35 0.10 0.33 0.20 4.80 Max. 1.75 0.25 0.51 0.25 5.00 5 2 2 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.150 .158 .050 BSC .228 .010 .016 8 0 - 8 .004 .244 .020 .050
3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 - 8 0.10 6.20 0.50 1.27
3 6
8
5
E
H
1
4
D A1 A SEATING PLANE B
-C-
h x 45 C
e
LEAD COPLANARITY ccc C
L
12
www.fairchildsemi.com
FAN5109 Rev. 1.0.4
FAN5109 Dual Bootstrapped 12V MOSFET Driver
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM FAST ActiveArrayTM FASTrTM BottomlessTM FPSTM Build it NowTM FRFETTM CoolFETTM GlobalOptoisolatorTM CROSSVOLTTM GTOTM DOMETM HiSeCTM EcoSPARKTM I2CTM E2CMOSTM i-LoTM EnSignaTM ImpliedDisconnectTM FACTTM IntelliMAXTM FACT Quiet SeriesTM Across the board. Around the world.TM The Power Franchise Programmable Active DroopTM
DISCLAIMER
ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC OPTOPLANARTM PACMANTM POPTM Power247TM PowerEdgeTM
PowerSaverTM PowerTrench QFET QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SerDesTM SILENT SWITCHER SMART STARTTM SPMTM StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6
SuperSOTTM-8 SyncFETTM TinyLogic TINYOPTOTM TruTranslationTM UHCTM UltraFET UniFETTM VCXTM WireTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I16
13
www.fairchildsemi.com
FAN5109 Rev. 1.0.4

▲Up To Search▲

Price & Availability of FAN5109MX

	To Download FAN5109MX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .